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HSC-ADC-EVALB-DCZ
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2009-05-15 HSC-ADC-FPGA-4,HSC-ADC-FPGA-8Z: High Speed De-Serialization Board
High speed ADC evaluation boards that support serial LVDS digital outputs also require the High Speed Deserialization board, HSC-ADC-FPGA. The high speed deserialization board captures up to four or eight channels of serial LVDS digital outputs and converts the data to standard parallel CMOS format. It supports quad analog-to-digital converterd (ADC) evaluation boards, enabling the user to connect to the Analog Devices FIFO-based data capture board (HSC-ADC-EVALB-DCZ-DC).
2009-05-15 HSC-ADC-EVALB-DCZ (Dual Channel): FIFO-Based Data Capture Kit
The HSC-ADC-EVALB-DCZ board is a FIFO-based data capture board that supports single, dual, and demulti-plexed SPI controllable ADC evaluation boards. This board is backwards compatible with ADC evaluation boards that are not SPI-controllable. It can simultaneously store the data from two ADC channels. The board is connected to the PC through a USB port and is used with ADC Analyzer to quickly evaluate the performance of high speed ADCs. Additional equipment needed includes an Analog Devices high speed ADC evaluation board, a signal source, and a clock source.
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