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Synopsys First to Announce DDR3 IP with Support for 2133 Mbps Data Rates and 1.35V DDR3L

2009年09月18日 ?? 收藏0
"The high-quality DesignWare DDR3/2 PHY and controller IP allowed us to achieve our design objectives and Synopsys provided Netronome with access to a team of DDR experts that was invaluable as we pushed towards the completion of our latest chip design."

"DDR3 SDRAMs are rapidly evolving to offer both higher performance and lower power consumption," said John Koeter, vice president of marketing for the Solutions Group at Synopsys. "By providing early access to enhancements in the JEDEC stand

ard DRAM roadmap, Synopsys is enabling designers to take full advantage of the latest advances in DDR technology. With a proven track record of over 200 DRAM interface design wins with more than 150 companies, Synopsys offers a low-risk path to working silicon."

The DesignWare DDR3/2 IP is a part of Synopsys' complete DesignWare DDR IP offering that consists of digital controllers, PHY and verification IP supporting DDR2, DDR3 and Mobile DDR. The comprehensive portfolio of DDR IP supports leading 130nm, 90nm, 65nm, 55nm and 45/40nm technologies. Synopsys helps lower integration risk by providing DDR IP solutions that have been implemented in hundreds of applications and are shipping in high-volume production.


The DesignWare DDR3/2 PHY supporting 2133 Mbps and 1.35V DDR3L is available now to early adopters. The DesignWare DDR3/2 controllers supporting 2133 Mbps and 1.35V DDR3L are anticipated to be generally available in October 2009. For more product information and to take a virtual tour of the Synopsys DDR lab to see how Synopsys verifies the IP, visit: http://www.synopsys.com/ddr

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