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28-Nanometer Design Capabilities to TSMC Reference Flow 10.0

2009年07月24日 ?? 收藏0
er Digital Implementation System, allowing early design stage identification, analysis and repair of potential manufacturing issues.

Other variation reduction techniques covered under the Cadence track of TSMC Reference Flow 10.0 include statistical static timing analysis (SSTA), placement optimization, advanced clock tree analysis and on-chip variation analysis. All of these techniques are dramatically accelerated through end-to-end support for multi-processor–based computing platforms.

Bu

ilding upon the Cadence NanoRoute? Router, which significantly boosts designer productivity and accelerates overall turnaround time, Cadence delivers a variety of other DFM techniques, including physical defect analysis, virtual CMP hot spot analysis, lithography process checking, advanced process modeling, and substrate noise analysis. All of these capabilities are fully integrated into the Encounter Digital Implementation System to allow the closest possible correlation between optimization and signoff.

Advanced Low-Power Design
Cadence introduced its Low-Power Design Solution more than two years ago and immediately incorporated its features into the TSMC Reference Flow 8.0. Since then, Cadence has updated its Low-Power Solution with new capabilities, including hierarchical support for the Si2 Common Power Format (CPF), pulse-latch, and dual-flop solutions. Because the Cadence Low-Power Solution is also seamlessly integrated into the Encounter Digital Implementation System, it provides low cost of ownership and an easy-to-use design environment for low-power design.

Cadence track of TSMC Reference Flow 10.0
Encounter Digital Implementation System (EDI System)
Cadence Low-Power Solution
Encounter RTL Compiler
Encounter Test
Encounter Conformal? (Low Power, Constraint Designer, LEC)
First Encounter Silicon Virtual Prototyping
NanoRoute Router
Encounter Timing System (with CeltIC? NDC)
Encounter Power System
QRC Extraction
Encounter Library Characterizer
Litho Ph


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Cadence? TSMC? 28nm?

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