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28-Nanometer Design Capabilities to TSMC Reference Flow 10.0

2009年07月24日 ?? 收藏0

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced that its suite of Cadence? Encounter? Digital Implementation System solutions, including design closure, low power, DFM, mixed signal, and signoff technologies, as well as System-In-Package design technology are included in TSMC Reference Flow 10.0. The RTL-to-GDSII design capabilities in the Cadence track enable designers to produce high-yielding, power-efficient designs for

the foundry’s most advanced manufacturing processes.

“Reference Flow 10.0 plays a critical role in design enablement for new process technologies,” said S.T. Juang, senior director of Design Infrastructure Marketing at TSMC. “The close collaboration with Cadence ensures needed tool enhancements are made ahead of time, as we are entering 28 nanometers.”

“Providing best-in-class solutions for today’s toughest design challenges and developing solutions ahead of the curve for tomorrow requires continuous innovation and tight collaboration with our customers and business partners,” said Dr. Chi Ping Hsu, vice president of digital implementation research and development at Cadence. “Working closely with TSMC helps ensure our leadership in low-power, mixed-signal, integrated DFM, advanced-node, and signoff technologies, and enables Cadence to provide a complete and predictable solution from RTL to final silicon.”

DFM, Digital Implementation and Analysis
A key contribution to Reference Flow 10.0 is the industry’s first context-aware electrical analysis of library cell and SOC designs. Using the award-winning Cadence Litho Electrical Analyzer, designers can electrically fine-tune library cells and accurately model electrical stress effects, thereby increasing product quality. In addition, the hierarchical Litho Physical Analyzer produces fast analysis of the physical manufacturability of nanometer-level devices. Both of these unique DFM capabilities are integrated into the Encount

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Cadence? TSMC? 28nm?


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