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HSC-ADC-FPGA-4,HSC-ADC-FPGA-8Z: High Speed De-Serialization Board

2009年05月15日 ?? 收藏0

High speed ADC evaluation boards that support serial LVDS digital outputs also require the High Speed Deserialization board, HSC-ADC-FPGA. The high speed deserialization board captures up to four or eight channels of serial LVDS digital outputs and converts the data to standard parallel CMOS format. It supports quad analog-to-digital converterd (ADC) evaluation boards, enabling the user to connect to the Analog Devices FIFO-based data capture board (HSC-ADC-EVALB-DCZ-DC).

Documentation

HSC-ADC-FPGA-4 Documentation (Rev. B, 11/2005) (pdf, 990,548 bytes)

HSC-ADC-FPGA-8Z Documentation (Rev. C, 11/2006) (pdf, 2,103,836 bytes)

HSC-ADC-FPGA-4-Gerber File (zip, 789,962 bytes)

HSC-ADC-FPGA-8Z-Gerber File (zip, 532,980 bytes)

HSC-ADC-FPGA-4 Verilog Code & Xilinx Programming Files (zip, 69,632 bytes)

HSC-ADC-FPGA-8Z Verilog Code & Xilinx Programming Files (zip, 963,896 bytes)

http://www.analog.com/en/analog-to-digital-converters/ad-converters/products/evaluation-boardstools/CU_High-Speed_ADC_FIFO_evaluation_tools/resources/fca.html


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