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瑞萨科技发布大容量片内闪存32位CISC微控制器H8SX/1657F [英]

2003年10月20日 ?? 收藏0
Renesas Technology Corp. announced the H8SX/1657F 32-bit CISC (Complex Instruction Set Computer) microcontroller incorporating 768 Kbytes of on-chip flash memory for use in optical storage devices and similar PC peripherals, OA devices, and consumer products.? Sample shipments will begin in December 2003 in Japan.

The H8SX/1657F is the second-phase product, following on from the initial-phase H8SX/1650, in the H8SX Family of microcontrollers incorporating an H8SX 32-bit CISC CPU core that u

ses a proprietary Renesas Technology architecture.

Features of the H8SX/1657F are summarized below.

(1)?Large 768-Kbyte on-chip flash memory
The H8SX/1657F is the first member of the H8SX Family with on-chip flash memory.? The flash memory is of large 768-Kbyte capacity and can be accessed in one cycle, enabling storage of large system programs that perform complex control functions, plus high-speed program processing.? The provision of flash memory allows construction of a single-chip system, and also helps reduce system cost and development time through its ability to be rewritten on-chip.

(2)?Provision of new peripheral function while maintaining compatibility with initial-phase H8SX/1650
The H8SX/1657F features pin arrangement compatibility with the initial-phase H8SX/1650 while incorporating a DMAC (Direct Memory Access Controller) as a new peripheral module that offers greater ease of use through such functions as an extended repeat area facility and offset addition, simplifying changeover from the H8SX/1650 to the H8SX/1657F for improved system performance.

(3)?32-bit H8SX CPU core and approximately 8 kilo-kinds instructions
The H8SX CPU core with 32-bit ALU and internal bus width offers 35 MIPS (Dhrystone 1.1) performance at a 35 MHz maximum operating frequency.? The instruction set includes new instructions in addition to those of the current H8S Family instruction set, and the number of addressing modes has been extended to 11. The instruction set consists of approximately 8 kilo-kinds instruction with combinations of byte, word, long-word and provides greater programming flexibility.

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