小组 > CPLD/FPGA > Altera MAX 10 FPGA > 【MAX10 DECA board开发板评测】之八--DDR3使用说明
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【MAX10 DECA board开发板评测】之八--DDR3使用说明


作者:youzizhile
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总积分:3002分
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发表于2016-04-15 15:40

本开发板使用的内存型号为MT41K256M16HA-125 ITE,为256M,16位总线宽度内存,支持以下几种操作速率:

使用FPGA开发DDR3的步骤

具体开发说明可以参考altera的官方资料:《External Memory Interface Handbook》

使用DECA自带的配置工具把需要的资源添加到工程中,同时生成了qsf引脚配置文件和系统top文件。

DDR3时钟特性:

打开quartus15.1软件后,在IP核中查找DDR3 控制器IP核。

查找对应的DDR3型号,应用到项目中,下图中标识黄色部分,若是没有对应的型号需要根据手册自己手动配置参数。

下面是根据开发板的器件信息系统IP核做的配置:

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avalon总线操作接口

module ddr3_example_if0 (

????????????? input? wire??????? pll_ref_clk,??????? //????? pll_ref_clk.clk

????????????? input? wire??????? global_reset_n,???? //???? global_reset.reset_n

????????????? input? wire??????? soft_reset_n,?????? //?????? soft_reset.reset_n

????????????? output wire??????? afi_clk,??????????? //????????? afi_clk.clk

????????????? output wire??????? afi_half_clk,?????? //???? afi_half_clk.clk

????????????? output wire??????? afi_reset_n,??????? //??????? afi_reset.reset_n

????????????? output wire??????? afi_reset_export_n, // afi_reset_export.reset_n

????????????? output wire [14:0] mem_a,????????????? //?? memory.mem_a

????????????? output wire [2:0]? mem_ba,???????????? //? .mem_ba

????????????? inout? wire [0:0]? mem_ck,???????????? //??mem_ck

????????????? inout wire [0:0]? mem_ck_n,?????????? //?????? .mem_ck_n

????????????? output wire [0:0]? mem_cke,??????????? //???.mem_cke

????????????? output wire [0:0] mem_cs_n,?????????? //???.mem_cs_n

????????????? output wire [1:0] mem_dm,???????????? //?? .mem_dm

????????????? output wire [0:0] mem_ras_n,????????? //? .mem_ras_n

????????????? output wire [0:0] mem_cas_n,????????? //???????????????? .mem_cas_n

????????????? output wire [0:0] mem_we_n,???? ??????//??????????????? .mem_we_n

????????????? output wire?? mem_reset_n,??????? //???????????????? .mem_reset_n

????????????? inout? wire [15:0] mem_dq,???????????? //???????????????? .mem_dq

????????????? inout? wire [1:0] mem_dqs,??????????? //???????????????? .mem_dqs

????????????? inout wire [1:0] mem_dqs_n,????????? //???????????????? .mem_dqs_n

????????????? output wire [0:0]? mem_odt,??????????? //???????????????? .mem_odt

????????????? output wire?? avl_ready,????????? //????????????? avl.waitrequest_n

????????????? input wire?? avl_burstbegin,???? //???????????????? .beginbursttransfer

????????????? input? wire [25:0] avl_addr,?????????? //???????????????? .address

????????????? output wire?? avl_rdata_valid,??? //???????????????? .readdatavalid

????????????? output wire [63:0] avl_rdata,????????? //???????????????? .readdata

????????????? input? wire [63:0] avl_wdata,??????? ??//???????????????? .writedata

????????????? input? wire [7:0]? avl_be,???????????? //???????????????? .byteenable

????????????? input? wire??????? avl_read_req,?????? //???????????????? .read

????????????? input? wire??????? avl_write_req,????? //???????????????? .write

????????????? input? wire [2:0]? avl_size,?????????? //???????????????? .burstcount

????????????? output wire???? local_init_done,??? //?????????? status.local_init_done

????????????? output wire?? local_cal_success,? //???????????????? .local_cal_success

????????????? output wire??? local_cal_fail,???? //??????????????? ?.local_cal_fail

????????????? output wire pll_mem_clk,??????? //????? pll_sharing.pll_mem_clk

????????????? output wire???? pll_write_clk,????? //???????????????? .pll_write_clk

????????????? output wire??????? pll_locked,???????? //???????????????? .pll_locked

????????????? output wire?? pll_capture0_clk,?? //???????????????? .pll_capture0_clk

????????????? output wire?? pll_capture1_clk??? //???????????????? .pll_capture1_clk

?????? );

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?编译时总是出错,还没有解决问题,正在查找解决办法。

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?MT41K256M16HA-125 ITE.pdf( 588KB ) ?该附件被下载次数 ?23
youzizhile 编辑于2016-04-15 15:52
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